Semiconductor integrated circuit chips (ICs) generally include a semiconductor substrate supporting at different locations on its surface circuits such as random access memory (RAM), arithmetic logic units (ALUs), multiplexers (MUXs), and addressable registers, interconnected by various data signal paths. These circuits are typically formed of various lower level logic circuits, or “cells,” such as NAND gates, NOR gates, inverter gates, and various types of latches and flip-flops (referenced generically “register cells”). The cells are typically interconnected such that the output of each connects, through respective signal paths, to inputs of other cells. Currently available large scale ICs can include millions of these cells.
The IC register cells can be edge-triggered devices, having a data input, a clock input and a data output. The clock is typically a two-level signal, having periodic edges, i.e., transitions, from one of a high or low voltage level to the other level.
The register cells may require the data signal to arrive and be stabilized at the data signal input prior to the clock edge arriving, by an amount of time not less than a given “set-up.” In addition, register cells may require the data signal to remain stable at the data signal input for a minimum “hold” time subsequent to the clock edge. If either the set-up or hold time is not met the register cell may fail to capture the data signal that was on its input.
At low clock rates there is typically no difficulty in arranging the cells to ensure that these set-up and hold times are met, for all of the register cells, over a wide range of process, voltage, or temperature (PVT) variations.
Meeting these time requirements has become more challenging, though, as clock frequencies have become higher. For example, current commercially available large scale ICs may operate at clock rates higher than approximately 2 GHz. At this example clock rate the successive clock edges are spaced in time by only 500 picoseconds, which results in a narrow allowable timing spread.
There are known IC design techniques intended to assist in the generation of IC layouts that meet these timing requirements, but each has significant costs and/or inherent shortcomings. The costs and shortcomings are seen particularly when attempting to determine the delay time through cells that have a small geometry and are located in a densely packed array of cells. The reason is that determining the delay for such cells must take into consideration the spacing and alignment of the active areas of that cell relative to the active areas of the neighboring cells. This spacing and alignment can be referred to as the “proximity context of the cell” or, alternatively, as the “cell proximity context.” Taking the cell proximity context into consideration when determining cell delays can exponentially increase the computational resources required for optimizing IC design.
FIG. 1 shows one binned distribution of a timing spread 12, and static current leakage variations 14, identified by example simulations of a number of instances of given standard cell within a given IC.
For example, one known technique for calculating the delays of densely packed, small geometry cells is to characterize their timings based on a set of fixed proximity contexts, and modeling the timing effects of proximity contexts by varying the RC time constant of the cell using a fastest (best) and slowest (worst) RC. Then, a slowest RC-based netlist and a pessimistic or slowest operating PVT timing corner are used to determine, or estimate, if setup constraints and timing slack are met, while a faster RC-based netlist and fastest operating PVT timing corner are used to determine, or estimate if hold constraints are met.
This RC-based approach, although perhaps practical in terms of the computational resources required, has significant shortcomings. One is that the technique may produce overly pessimistic timing and power values for each cell. The resulting IC design, being based on these pessimistic timing and power values, may occupy a larger die area, and/or burn more dynamic power. In addition, ICs incorporating the RC-based design may impact the yield of ICs due to skewing between data and clock paths, not ascertainable from RC-based design.
As another example illustrating shortcomings of known techniques to estimate cell delay and leakage of tightly packed, small geometry cells, one of these known methods is to exhaustively model the cell timing, and leakage for each and every possible context. The exhaustive model information can then accurately estimate, using the multiple context-based cell timings, all timing skews in all setup/hold paths, for various PVT corners of interest. However, ASICs today may have millions of gates with thousands of different standard cells. The computational resources required for this exhaustive modeling approach render it impractical for many applications.